RF PCB Quality Control — AOI, TDR Sampling, Microsection and Batch Traceability
RF PCB quality control differs from standard digital PCB inspection in one important way: electrical continuity is not the same as RF performance. A board can pass 100% continuity and isolation testing while still having an impedance error, a marginal via structure, or a material lot variance that only becomes visible under TDR or microsection inspection. This guide covers what inspection methods apply at each stage of an RF PCB order — from prototype through repeat production — and what to specify when placing an order.
Table of Contents
Inspection Methods and Scope
| Inspection Type | Scope / Sampling | What It Catches |
|---|---|---|
| AOI (Automated Optical Inspection) | 100% of panels, every run | Trace width/spacing violations, open/short circuits, etching defects |
| TDR impedance | Per-panel or per-lot, per spec | Dk variation, trace width error, stackup drift |
| Microsection FAI | 1 sample per lot, or per requirement | Copper plating thickness, void %, annular ring, registration |
| Continuity/isolation (E-test) | 100% of boards | Open circuits, shorts — baseline pass/fail |
| X-ray inspection | Sample or 100% for high-power/high-reliability | Internal via voids, hidden misalignment, BGA solder quality |
| Impedance witness coupon | Per panel, alongside production boards | Non-destructive impedance verification |
AOI and E-test are baseline checks that apply to every board regardless of application — they catch manufacturing defects but do not verify RF performance. TDR and microsection are the inspections that specifically verify RF-relevant characteristics: TDR confirms the finished board’s actual impedance matches the design target, and microsection confirms the internal via and copper structure meets the specified quality level. For RF designs, both should be part of the standard inspection plan, not an optional add-on.
Impedance Witness Coupons
A witness coupon is a small test structure fabricated alongside the production boards on the same panel, using the same process and material lot, specifically for TDR measurement. This allows impedance verification without cutting into a production board — the coupon result represents the panel’s actual impedance because it was built under identical conditions. For controlled impedance designs, specify a witness coupon on every panel rather than relying on sampling from finished boards.
IPC Class 2 vs Class 3 Inspection Requirements
| Requirement | IPC Class 2 (Commercial) | IPC Class 3 (Aerospace/Defense) |
|---|---|---|
| TDR impedance sampling | Per drawing, typically per-lot | Per-panel standard, ±5% common |
| Microsection FAI | On request | Standard, every lot |
| Void limit per via | 10% maximum | 5% maximum |
| Annular ring (inner layer) | Breakout permitted | No breakout — confirmed ring required |
| Material lot traceability | Often on request | Standard, documented chain of custody |
The inspection requirements scale with IPC Class, not just the material or design complexity. A commercial RF board and an aerospace RF board using identical material and stackup will have different inspection scope if one specifies Class 2 and the other Class 3 — the electrical design does not change, but the verification burden does. See our aerospace and defense PCB material qualification guide for the full documentation checklist that accompanies Class 3 inspection.
Prototype-to-Batch Consistency
| Prototype-to-Batch Risk | How to Control It |
|---|---|
| Material lot variation between prototype and production | Request single-lot material for phased array or tight-tolerance designs |
| Different process settings between small and large panel runs | Confirm same process parameters apply regardless of order size |
| Etching tolerance drift at higher panel utilization | Specify trace width tolerance explicitly — don't assume prototype tolerance carries over |
| Surface finish batch-to-batch consistency | Request ENIG thickness verification data with production lots |
| Missing impedance test on repeat orders | Specify TDR verification as a standing PO requirement, not one-time |
A prototype that passes every inspection does not guarantee the production run will match — this is one of the most common gaps in RF PCB quality control. Material lot changes, different panel utilization at production volume, and process drift between small and large runs can all introduce variation that was not present in the prototype. For designs where element-to-element or board-to-board consistency matters — phased arrays, multi-channel receivers — specify single-lot material and standing TDR verification requirements on the purchase order, not just the initial prototype order.
What to Specify on Your Fabrication Drawing
- TDR impedance requirement explicitly — target, tolerance, and whether witness coupon or production board sampling is required
- Microsection FAI requirement and frequency — per lot, or per order, depending on your reliability requirements
- IPC Class — 2 or 3 — stated explicitly, not assumed as default
- Material lot traceability requirement if your application requires anomaly investigation capability
- X-ray inspection requirement for any high-power thermal via arrays or BGA/fine-pitch components
- Standing inspection requirements for repeat orders — specify that production runs receive the same inspection scope as the initial prototype, not a reduced scope by default
RF PCB Quality Control — Q&A
Common questions about inspection methods, witness coupons, IPC Class requirements, and prototype-to-batch consistency for RF PCB.
Does a PCB passing continuity test mean the RF performance is correct?
No. E-test confirms electrical connections but doesn't verify impedance, insertion loss, or via structure quality. A board can pass 100% continuity testing while still having an impedance error or material lot variance only visible under TDR or microsection inspection.
What is an impedance witness coupon?
A test structure built alongside production boards on the same panel, same process, same material lot, specifically for TDR measurement — verifies impedance without cutting into production boards, representing the panel's actual build conditions.
What is the difference between IPC Class 2 and Class 3 inspection requirements?
Class 3 requires stricter inspection: microsection FAI becomes standard every lot, void limits tighten from 10% to 5%, TDR sampling moves to per-panel, and material lot traceability becomes standard. Electrical design doesn't change — verification burden does.
Why might a production run not match a prototype that passed all tests?
Material lot changes, different panel utilization, and process drift between small and large runs can introduce variation not in the original prototype. For phased arrays or multi-channel designs, specify single-lot material and standing TDR requirements on the PO.
TDR Verification Every Lot — Not Just Prototype
Material lot certificates, microsection FAI, and impedance witness coupons available as standard. IPC Class 2 standard, Class 3 on request. Same inspection scope for prototype and production runs.
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